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| Digitally Programmable Sensor Signal Amplifier with EMI Filters AD8556 FEATURES EMI filters at input pins Specified from -40C to +140C Low offset voltage: 10 V max Low input offset voltage drift: 65 nV/C max High CMRR: 94 dB min Digitally programmable gain and output offset voltage Programmable output clamp voltage Open and short wire fault detection Low-pass filtering Single-wire serial interface Stable with any capacitive load SOIC_N and LFCSP_VQ packages 2.7 V to 5.5 V operation www..com APPLICATIONS Automotive sensors Pressure and position sensors Precision current sensing Strain gages FUNCTIONAL BLOCK DIAGRAM DIGIN VDD VCLAMP VDD EMI FILTER LOGIC VDD A5 1 +IN 2 DAC OUT -IN VSS 3 VSS 3 VPOS EMI FILTER 1 +IN 2 A1 R5 R2 P4 R7 OUT -IN VSS P2 EMI FILTER R3 P1 VDD A3 1 +IN 2 VDD 3 VDD RF OUT -IN VSS EMI FILTER 1 +IN 2 -IN A4 OUT 3 VOUT -IN 1 +IN VNEG A2 OUT 3 R1 R4 P3 R6 VSS EMI FILTER 2 +IN -IN VSS AD8556 FILT/DIGOUT VSS Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c) 2005 Analog Devices, Inc. All rights reserved. 05448-053 AD8556 www..com TABLE OF CONTENTS Specifications..................................................................................... 4 Absolute Maximum Ratings............................................................ 6 Thermal Resistance ...................................................................... 6 ESD Caution.................................................................................. 6 Pin Configurations and Function Descriptions ........................... 7 Typical Performance Characteristics ............................................. 8 Theory of Operation ...................................................................... 16 Gain Values.................................................................................. 17 Open Wire Fault Detection....................................................... 18 Shorted Wire Fault Detection................................................... 18 Floating VPOS, VNEG, or VCLAMP Fault Detection ......... 18 Device Programming................................................................. 18 EMI/RFI Performance ................................................................... 24 Outline Dimensions ....................................................................... 26 Ordering Guide .......................................................................... 26 REVISION HISTORY 5/05--Revision 0: Initial Version Rev. 0 | Page 2 of 28 AD8556 www..com GENERAL DESCRIPTION The AD8556 is a zero-drift, sensor signal amplifier with digitally programmable gain and output offset. Designed to easily and accurately convert variable pressure sensor and strain bridge outputs to a well-defined output voltage range, the AD8556 accurately amplifies many other differential or single-ended sensor outputs. The AD8556 uses the ADI patented low noise auto-zero and DigiTrim(R) technologies to create an incredibly accurate and flexible signal processing solution in a very compact footprint. Gain is digitally programmable in a wide range from 70 to 1,280 through a serial data interface. Gain adjustment can be fully simulated in-circuit and then permanently programmed with reliable polyfuse technology. Output offset voltage is also digitally programmable and is ratiometric to the supply voltage. AD8556 also features internal EMI filters on the VNEG, VPOS, FILT and VCLAMP pins. In addition to extremely low input offset voltage, low input offset voltage drift, and very high dc and ac CMRR, the AD8556 also includes a pull-up current source at the input pins and a pull-down current source at the VCLAMP pin. This allows open wire and shorted wire fault detection. A low-pass filter function is implemented via a single low cost external capacitor. Output clamping set via an external reference voltage allows the AD8556 to drive lower voltage ADCs safely and accurately. When used in conjunction with an ADC referenced to the same supply, the system accuracy becomes immune to normal supply voltage variations. Output offset voltage can be adjusted with a resolution of better than 0.4% of the difference between VDD and VSS. A lockout trim after gain and offset adjustment further ensures field reliability. The AD8556 is fully specified from -40C to +140C. Operating from single-supply voltages of 2.7 V to 5.5 V, the AD8556 is offered in the 8-lead SOIC_N, and 4 mm x 4 mm 16-lead LFCSP_VQ. Rev. 0 | Page 3 of 28 AD8556 w w w . D a SPECIFICATIONS VDD = 5.0 V, VSS = 0.0 V, VCM = 2.5 V, VO = 2.5 V, -40C TA +140C, unless otherwise specified. Table 1. Electrical Specifications Parameter INPUT STAGE Input Offset Voltage Input Offset Voltage Drift Input Bias Current Symbol VOS TCVOS IB Conditions -40C TA +125C -40C TA +140C TA = 25C -40C TA +125C -40C TA +140C TA = 25C -40C TA +125C -40C TA +140C VCM = 2.1 V to 2.9 V, AV = 70 VCM = 2.1 V to 2.9 V, AV = 1,280 VO = 0.2 V to 3.4 V VO = 0.2 V to 4.8 V Second stage gain = 17.5 to 100 Second stage gain = 140 to 200 Second stage gain = 17.5 to 100 Second stage gain = 140 to 200 RF RF Temperature Coefficient DAC Accuracy Ratiometricity Output Offset Temperature Coefficient VCLAMP Input Bias Current 14 38 Min Typ 2 3 25 49 Max 10 12 65 54 58 60 2.5 3.0 4.0 2.9 Unit V V nV/C nA nA nA nA nA nA V dB dB ppm ppm % % ppm/C ppm/C k ppm/C % ppm mV ppm FS/C ppm FS/C nA nA nA V mV mA mV V Input Offset Current IOS 0.2 Input Voltage Range Common-Mode Rejection Ratio Linearity Differential Gain Accuracy Differential Gain Temperature Coefficient CMRR 2.1 80 94 92 112 20 1,000 0.35 0.5 7 10 18 600 0.2 50 5 3.3 1.6 2.5 20 40 22 AV = 70, offset codes = 8 to 248 AV = 70, offset codes = 8 to 248 AV = 70, offset codes = 8 to 248 -40C TA +125C -40C TA +140C TA = 25C, VCLAMP = 5 V -40C TA +125C, VCLAMP = 5 V -40C TA +140C, VCLAMP = 5 V 1.2 0.6 35 15 25 200 500 550 4.94 3 7 10 20 Input Voltage Range OUTPUT BUFFER STAGE Buffer Offset Short-Circuit Current Output Voltage, Low Output Voltage, High POWER SUPPLY Supply Current ISC VOL VOH ISY 5 RL = 10 k to 5 V RL = 10 k to 0 V -40C TA +125C, VO = 2.5 V, VPOS = VNEG = 2.5 V, VDAC code = 128; -40C TA +140C, VO = 2.5 V, VPOS = VNEG = 2.5 V, VDAC Code = 128 AV = 70 10C < TPROG < 40C, supply capable of driving 250 mA 4.94 2.0 2.7 2.78 mA mA dB V Power Supply Rejection Ratio Supply Voltage Required During Programming PSRR 109 5.0 125 5.25 5.5 Rev. 0 | Page 4 of 28 AD8556 www..com Parameter DYNAMIC PERFORMANCE Gain Bandwidth Product Symbol GBP Conditions First gain stage, TA = 25C Second gain stage, TA = 25C Output buffer stage, TA = 25C AV = 70, RL = 10 k, CL = 100 pF, TA = 25C To 0.1%, AV = 70, 4 V output step, TA = 25C TA = 25C, f = 1 kHz f = 0.1 Hz to 10 Hz, TA = 25C VIN = 16.75 mV rms, f = 1 kHz, AV = 100, TA = 25C Min Typ 2 8 1.5 1.2 8 32 0.5 -100 2 Max Unit MHz MHz MHz V/s s nV/Hz V p-p dB A s s s V V V V Output Buffer Slew Rate Settling Time NOISE PERFORMANCE Input Referred Noise Low Frequency Noise Total Harmonic Distortion DIGITAL INTERFACE Input Current DIGIN Pulse Width to Load 0 DIGIN Pulse Width to Load 1 Time Between Pulses at DIGIN DIGIN Low DIGIN High DIGOUT Logic 0 DIGOUT Logic 1 SR ts en p-p THD tw0 tw1 tws TA = 25C TA = 25C TA = 25C TA = 25C TA = 25C TA = 25C TA = 25C 0.05 50 10 4 10 1 1 4 Rev. 0 | Page 5 of 28 AD8556 www..com ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Supply Voltage Input Voltage Differential Input Voltage1 Output Short-Circuit Duration to VSS or VDD Storage Temperature Range Operating Temperature Range Junction Temperature Range Lead Temperature Range 1 Rating 6V VSS - 0.3 V to VDD + 0.3 V 5.0 V Indefinite -65C to +150C -40C to +150C -65C to +150C 300C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE JA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 3. Thermal Resistance Package Type 8-Lead SOIC_N (R) 16-Lead LFCSP_VQ (CP) 1 Differential input voltage is limited to 5.0 V or the supply voltage, whichever is less. JA1 158 44 JC 43 31.5 Unit C/W C/W JA is specified for the worst-case conditions, that is, JA is specified for device soldered in circuit board for LFCSP_VQ package. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. 0 | Page 6 of 28 AD8556 www..com PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 16 AVDD 15 DVDD 14 AVSS VDD 1 FILT/DIGOUT 2 DIGIN 3 VNEG 4 8 AD8556 TOP VIEW (Not to Scale) VSS VOUT 05448-002 7 6 5 VCLAMP VPOS 13 DVSS NC 1 FILT/DIGOUT 2 NC 3 DIGIN 4 PIN 1 INDICATOR 12 VOUT 11 NC 10 VCLAMP 9 AD8556 TOP VIEW Figure 2. 8-Lead SOIC_N Pin Configuration NC NC 5 VNEG 6 NC 7 VPOS 8 NC = NO CONNECT Figure 3.16-Lead LFCSP_VQ Pin Configuration Table 4. Pin Function Descriptions SOIC_N 1 2 Pin No. LFCSP_VQ 2 Mnemonic VDD FILT/DIGOUT Description Positive Supply Voltage. Unbuffered Amplifier Output in Series with a Resistor RF. Adding a capacitor between FILT and VDD or VSS implements a low-pass filtering function. In read mode, this pin functions as a digital output. Digital Input. Negative Amplifier Input (Inverting Input). Positive Amplifier Input (Noninverting Input). Set Clamp Voltage at Output. Buffered Amplifier Output. Buffered version of the signal at the FILT/DIGOUT pin. In read mode, VOUT is a buffered digital output. Negative Supply Voltage. Negative Supply Voltage. Positive Supply Voltage. Do Not Connect. 3 4 5 6 7 8 4 6 8 10 12 DIGIN VNEG VPOS VCLAMP VOUT VSS DVSS, AVSS DVDD, AVDD NC 13, 14 15, 16 1, 3, 5, 7, 9, 11 Rev. 0 | Page 7 of 28 05448-003 AD8556 www..com TYPICAL PERFORMANCE CHARACTERISTICS 100 N: 363, MEAN: -0.389938, SD: 1.65684 25 VSY = 5V NUMBER OF AMPLIFIERS 05448-004 80 20 HITS 60 15 40 10 20 5 -5 0 VOS 5V (V) 5 10 0 10 20 30 TCVOS (nV/C) 40 MORE Figure 4. Input Offset Voltage Distribution 2.0 1.5 1.0 0.5 0 VS = 5V TA = 25C Figure 7. TCVOS at VSY = 5 V VSY = 5V 1.9 BUFFER OFFSET VOLTAGE (mV) 1.7 1.5 1.3 1.1 0.9 0.7 05448-009 05448-010 VOUT = 0.3V VOSi (V) -0.5 -1.0 -1.5 -2.0 -2.5 05448-005 VOUT = 4.7V -3.0 1.5 2.0 2.5 VCM (V) 3.0 3.5 0.5 -50 -25 0 25 50 75 TEMPERATURE (C) 100 125 150 Figure 5. Input Offset Voltage vs. Common-Mode Voltage 10 8 6 100 Figure 8. Output Buffer Offset vs. Temperature VSY = 5V VSY = 5V INPUT OFFSET VOLTAGE (V) 4 2 0 -2 -4 -6 -8 05448-006 INPUT BIAS CURRENT (nA) 10 -10 -50 -25 0 25 50 75 TEMPERATURE (C) 100 125 150 1 -50 -25 0 25 50 75 TEMPERATURE (C) 100 125 150 Figure 6. Input Offset Voltage vs. Temperature Figure 9. Input Bias Current at VPOS, VNEG vs. Temperature Rev. 0 | Page 8 of 28 05448-007 0 -10 0 AD8556 www..com 100 IB- VSY = 5 TA = 25C 1000 VS = 5V VCLAMP CURRENT (nA) IB+ +125C +25C 100 -40C IB (nA) 10 05448-011 0 1 2 3 VCM (V) 4 5 6 0 1 2 3 4 VCLAMP VOLTAGE (V) 5 6 Figure 10. Input Bias Current at VPOS, VNEG vs. Common-Mode Voltage 0.8 0.6 Figure 13. VCLAMP Current over Temperature at VS = 5 V vs. VCLAMP Voltage 3.0 VSY = 5V TA = 25C INPUT OFFSET CURRENT (nA) 0.5 2.5 SUPPLY CURRENT (mA) 0.3 0.2 0 -0.2 -0.3 -0.5 -0.6 05448-012 2.0 1.5 1.0 0.5 -25 0 25 50 75 TEMPERATURE (C) 100 125 150 0 1 2 3 4 SUPPLY VOLTAGE (V) 5 6 Figure 11. Input Offset Current vs. Temperature 2.5 2.5 2.3 Figure 14. Supply Current (ISY) vs. Supply Voltage VS = 5.5V VSY = 5V DIGITAL INPUT CURRENT (A) 2.0 2.1 1.5 SUPPLY CURRENT (mA) 1.9 1.7 1.5 1.3 1.1 0.9 0.7 1.0 0.5 05448-013 0 1 2 3 4 DIGITAL INPUT VOLTAGE (V) 5 6 -25 0 25 50 75 TEMPERATURE (C) 100 125 150 Figure 12. Digital Input Current vs. Digital Input Voltage (Pin 4) Figure 15. Supply Current (ISY) vs. Temperature Rev. 0 | Page 9 of 28 05448-016 0 0.5 -50 05448-015 -0.8 -50 0 05448-014 1 10 AD8556 www..com VS = 2.5V GAIN = 70 VS = 2.5V GAIN = 70 120 VOLTAGE NOISE DENSITY (nV/ Hz) 05448-017 CMRR (dB) 60 50 40 30 20 10 0 5 FREQUENCY (kHz) 10 05448-020 05448-022 80 40 0 100 1k 10k FREQUENCY (Hz) 100k 1M Figure 16. CMRR vs. Frequency Figure 19. Input Voltage Noise Density vs. Frequency (0 Hz to 10 kHz) VS = 2.5V GAIN = 1280 VS = 2.5V GAIN = 70 VOLTAGE NOISE DENSITY (nV/ Hz) 120 35 30 25 20 15 10 5 0 250 FREQUENCY (kHz) 500 05448-021 CMRR (dB) 80 40 1k 10k FREQUENCY (Hz) 100k 1M Figure 17. CMRR vs. Frequency VSY = 5V 05448-018 0 100 Figure 20. Input Voltage Noise Density vs. Frequency (0 Hz to 500 kHz) 145 135 125 GAIN = 1280 GAIN = 800 GAIN = 400 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 VS = 2.5V GAIN = 1000 CMRR (dB) 105 95 85 05448-019 GAIN = 70 GAIN = 200 GAIN = 100 75 -50 -25 0 25 50 75 TEMPERATURE (C) 100 125 150 NOISE (V) 115 TIME (1s/DIV) Figure 18. CMRR vs. Temperature at Different Gains Figure 21. Low Frequency Input Voltage Noise (0.1 Hz to 10 Hz) Rev. 0 | Page 10 of 28 AD8556 www..com VS = 2.5V 8 4 GAIN (dB) 0 -4 -8 1k 10k 100k FREQUENCY (Hz) 1M 10M 05448-026 05448-028 05448-027 Figure 22. Low Frequency Input Voltage Noise (0.1 Hz to 10 Hz) VS = 2.5V CL = 40PF Figure 25. Output Buffer Gain vs. Frequency 60 VS = 2.5V RS 50 OUTPUT BUFFER GAIN = 1280 60 RS = 0 CL CLOSED-LOOP GAIN (dB) 40 GAIN = 70 20 OVERSHOOT (%) 40 30 RS = 10 20 RS = 50 10 RS = 100 1 10 LOAD CAPACITANCE (nF) 100 RS = 20 0 05448-024 1k 10k 100k FREQUENCY (Hz) 1M 0 0.1 Figure 23. Closed-Loop Gain vs. Frequency Measured at Filter Pin VS = 2.5V GAIN = 1280 60 Figure 26. Output Buffer Positive Overshoot 60 VS = 2.5V RS 50 CL RS = 0 CLOSED-LOOP GAIN (dB) 40 GAIN = 70 20 OVERSHOOT (%) 40 30 RS = 10 20 RS = 20 0 10 RS = 100 1.0 10.0 LOAD CAPACITANCE (nF) RS = 50 100.0 05448-025 1k 10k 100k FREQUENCY (Hz) 1M 0 0.1 Figure 24. Closed-Loop Gain vs. Frequency Measured at Output Pin Figure 27. Output Buffer Negative Overshoot Rev. 0 | Page 11 of 28 AD8556 www..com 1.000 VS = 2.5V VDD - OUTPUT VOLTAGE (V) 6 0.100 VOLTAGE (1V/DIV) SOURCE SUPPLY VOLTAGE 5 4 3 2 1 SINK 0.010 0.10 1.00 LOAD CURRENT (mA) 10.0 05448-029 0.001 0.01 0 TIME (100s/DIV) Figure 28. Output Voltage to Supply Rail vs. Load Current 15 12 Figure 31. Power-On Response at 125C OUTPUT SHORT CIRCUIT (mA) 9 6 3 0 -3 -6 -9 -12 -50 SINK 5V 6 SUPPLY VOLTAGE VOLTAGE (1V/DIV) 5 4 3 2 1 SOURCE 5V -25 0 25 50 75 100 TEMPERATURE (C) 125 150 175 05448-030 -15 -75 0 TIME (100s/DIV) Figure 29. Output Short-Circuit vs. Temperature 150 SUPPLY VOLTAGE 4 2 145 140 135 Figure 32. Power-On Response at -40C VS = 2.7V TO 5.5V VOLTAGE 0 3 2 1 0 TIME (100s/DIV) PSRR (dB) 130 125 120 115 110 VOUT 05448-031 105 -50 -25 0 25 50 75 TEMPERATURE (C) 100 125 150 05448-034 100 -75 Figure 30. Power-On Response at 25C Figure 33. PSRR vs. Temperature Rev. 0 | Page 12 of 28 05448-033 VOUT 05448-032 VOUT AD8556 www..com 140 120 100 80 60 40 20 0 0.01 VOUT (1V/DIV) VS = 2.7V TO 2.5V T VS = 2.5V GAIN = 70 CL = 100pF PSRR (dB) 2 05448-035 0.1 1 FREQUENCY (kHz) 10 100 TIME (10s/DIV) Figure 34. PSRR vs. Frequency Figure 37. Large Signal Response T VS = 2.5V GAIN = 70 CL = 0.1F FIN = 10kHz T VS = 2.5V GAIN = 70 CL = 0.05F VOUT (50mV/DIV) VOUT (1V/DIV) 2 2 05448-036 TIME (100s/DIV) TIME (10s/DIV) Figure 35. Small Signal Response 1k Figure 38. Large Signal Response VSY = 2.5V AV = 70 T VS = 2.5V GAIN = 70 CL = 100pF FIN = 1kHz 100 VOUT (50mV/DIV) 2 IMPEDANCE () 10 05448-037 1 TIME (100s/DIV) 10 100 FREQUENCY (kHz) 1M Figure 36. Small Signal Response Figure 39. Output Impedance vs. Frequency Rev. 0 | Page 13 of 28 05448-040 1 0.1 05448-039 05448-038 AD8556 www..com 0V 1 VIN VIN 0V 1 0V 2 VOUT VOUT 0V 2 05448-041 CH1 50.0mV CH2 2.00V M 1.00s A CH1 -21.0mV CH1 10.0mV CH2 2.00V M 4.00s A CH1 8.40mV Figure 40. Negative Overload Recovery (Gain = 70) Figure 43. Positive Overload Recovery (Gain = 1280) GAIN = 70 OFFSET = 128 VS = 2.5V 1 VIN 0V 1 +V 4V pp 0.1F 6 8 7 20.5 294 4 5 1 VOUT 0V 2 DUT 10k 05448-042 0.1F -V 1k 10k 05448-045 2 OUT CH1 2.00mV CH2 2.00mV M 1.00s A CH1 40.0mV CH1 50.0mV CH2 2.00V M 1.00s A CH1 57.0mV Figure 41. Positive Overload Recovery (Gain = 70) Figure 44. Settling Time 0.1% GAIN = 70 OFFSET = 128 VS = 2.5V 0V 1 0V 1 VIN +V 4V pp 0.1F 6 8 7 20.5 294 4 5 1 0V 2 -2.5V DUT 10k 05448-043 0.1F -V 1k 10k 05448-046 0V 2 CH1 2.00mV CH2 2.00mV OUT M 1.00s A CH1 40.0mV CH1 10.0mV CH2 2.00V M 4.00s A CH1 -9.40mV Figure 42. Negative Overload Recovery (Gain = 1280) Figure 45. Settling Time 0.01% Rev. 0 | Page 14 of 28 05448-044 AD8556 www..com 1.00 0.50 VS = 2.5V 0.20 THD (%) 0.10 0.05 0.02 0.01 20 50 100 200 500 1k 2k FREQUENCY (Hz) 5k 10k 20k Figure 46. THD vs. Frequency 05448-047 Rev. 0 | Page 15 of 28 AD8556 www..com THEORY OF OPERATION A1, A2, R1, R2, R3, P1, and P2 form the first gain stage of the differential amplifier. A1 and A2 are auto-zeroed op amps that minimize input offset errors. P1 and P2 are digital potentiometers, guaranteed to be monotonic. Programming P1 and P2 allows the first stage gain to be varied from 4.0 to 6.4 with 7-bit resolution (see Table 5 and Equation 1), giving a fine gain adjustment resolution of 0.37%. R1, R2, R3, P1, and P2 each have a similar temperature coefficient, so the first stage gain temperature coefficient is lower than 100 ppm/C. positive swing to be limited. The maximum output current is limited between 5 mA to 10 mA. An 8-bit digital-to-analog converter (DAC) is used to generate a variable offset for the amplifier output. This DAC is guaranteed to be monotonic. To preserve the ratiometric nature of the input signal, the DAC references are driven from VSS and VDD, and the DAC output can swing from VSS (Code 0) to VDD (Code 255). The 8-bit resolution is equivalent to 0.39% of the difference between VDD and VSS, for example, 19.5 mV with a 5 V supply. The DAC output voltage (VDAC) is given approximately by 6.4 GAIN1 4 x 4 Code 127 (1) A3, R4, R5, R6, R7, P3, and P4 form the second gain stage of the differential amplifier. A3 is also an auto-zeroed op amp that minimizes input offset errors. P3 and P4 are digital potentiometers, which allow the second stage gain to be varied from 17.5 to 200 in eight steps (see Table 6). R4, R5, R6, R7, P3, and P4 each have a similar temperature coefficient, so the second stage gain temperature coefficient is lower than 100 ppm/C. RF together with an external capacitor, connected between FILT/DIGOUT and VSS or VDD, form a low-pass filter. The filtered signal is buffered by A4 to give a low impedance output at VOUT. RF is nominally 18 k, allowing an 880 Hz low-pass filter to be implemented by connecting a 10 nF external capacitor between FILT/DIGOUT and VSS, or between FILT/DIGOUT and VDD. If low-pass filtering is not needed, the FILT/DIGOUT pin must be left floating. A5 implements a voltage buffer, which provides the positive supply to A4, the amplifier output buffer. Its function is to limit VOUT to a maximum value, useful for driving analog-to-digital converters (ADC) operating on supply voltages lower than VDD. The input to A5, VCLAMP, has a very high input resistance. It should be connected to a known voltage and not left floating. However, the high input impedance allows the clamp voltage to be set using a high impedance source, such as, a potential divider. If the maximum value of VOUT does not need to be limited, VCLAMP should be connected to VDD. A4 implements a rail-to-rail input and output unity-gain voltage buffer. The output stage of A4 is supplied from a buffered version of VCLAMP instead of VDD, allowing the Code + 0.5 VDAC (VDD - VSS ) + VSS 256 Where the temperature coefficient of VDAC is lower than 200 ppm/C. The amplifier output voltage (VOUT) is given by VOUT = GAIN (VPOS - VNEG ) + VDAC (2) (3) where GAIN is the product of the first and second stage gains. VDD VDD VNEG A1 R4 R1 VSS P1 R3 VDD P2 R2 R5 VDD VSS DAC 05448-001 VCLAMP A5 P3 R6 VSS VDD RF A4 VSS R7 P4 FILT/ DIGOUT VDD VOUT A3 VSS A2 VPOS VSS Figure 47. Functional Schematic Rev. 0 | Page 16 of 28 AD8556 www..com GAIN VALUES Table 5. First Stage Gain vs. First Stage Gain Code First Stage Gain Code 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 First Stage Gain 4.000 4.015 4.030 4.045 4.060 4.075 4.090 4.105 4.120 4.135 4.151 4.166 4.182 4.197 4.213 4.228 4.244 4.260 4.276 4.291 4.307 4.323 4.339 4.355 4.372 4.388 4.404 4.420 4.437 4.453 4.470 4.486 First Stage Gain Code 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 First Stage Gain 4.503 4.520 4.536 4.553 4.570 4.587 4.604 4.621 4.638 4.655 4.673 4.690 4.707 4.725 4.742 4.760 4.778 4.795 4.813 4.831 4.849 4.867 4.885 4.903 4.921 4.939 4.958 4.976 4.995 5.013 5.032 5.050 First Stage Gain Code 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 First Stage Gain 5.069 5.088 5.107 5.126 5.145 5.164 5.183 5.202 5.221 5.241 5.260 5.280 5.299 5.319 5.339 5.358 5.378 5.398 5.418 5.438 5.458 5.479 5.499 5.519 5.540 5.560 5.581 5.602 5.622 5.643 5.664 5.685 First Stage Gain Code 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 First Stage Gain 5.706 5.727 5.749 5.770 5.791 5.813 5.834 5.856 5.878 5.900 5.921 5.943 5.965 5.988 6.010 6.032 6.054 6.077 6.099 6.122 6.145 6.167 6.190 6.213 6.236 6.259 6.283 6.306 6.329 6.353 6.376 6.400 Table 6. Second Stage Gain and Gain Ranges vs. Second Stage Gain Code Second Stage Gain Code 0 1 2 3 4 5 6 7 Second Stage Gain 17.5 25 35 50 70 100 140 200 Minimum Combined Gain 70 100 140 200 280 400 560 800 Maximum Combined Gain 112 160 224 320 448 640 896 1280 Rev. 0 | Page 17 of 28 AD8556 www..com OPEN WIRE FAULT DETECTION The inputs to A1 and A2, VNEG and VPOS, each have a comparator to detect whether VNEG or VPOS exceeds a threshold voltage, nominally VDD - 2.0 V. If (VNEG > VDD - 2.0 V) or (VPOS > VDD - 2.0 V), VOUT is clamped to VSS. The output current limit circuit is disabled in this mode, but the maximum sink current is approximately 10 mA when VDD = 5 V. The inputs to A1 and A2, VNEG and VPOS, are also pulled up to VDD by currents IP1 and IP2. These are both nominally 49 nA and matched to within 3 nA. If the inputs to A1 or A2 are accidentally left floating, as with an open wire fault, IP1 and IP2 pull them to VDD which would cause VOUT to swing to VSS, allowing this fault to be detected. It is not possible to disable IP1 and IP2, nor the clamping of VOUT to VSS, when VNEG or VPOS approaches VDD. FLOATING VPOS, VNEG, OR VCLAMP FAULT DETECTION A floating fault condition at the VPOS, VNEG, or VCLAMP pins is detected by using a low current to pull a floating input into an error voltage range, defined in the previous section. In this way, the VOUT pin is shorted to VSS when a floating input is detected. Table 8 lists the currents used. Table 8. Floating Fault Detection at VPOS, VNEG, and VCLAMP Pin VPOS VNEG VCLAMP Typical Current 49 nA pull-up 49 nA pull-up 0.2 A pull-down Goal of Current Pull VPOS above VINH Pull VNEG above VINH Pull VCLAMP below VCLL SHORTED WIRE FAULT DETECTION The AD8556 provides fault detection in the case where VPOS, VNEG, or VCLAMP shorts to VDD and VSS. Figure 48 shows the voltage regions at VPOS, VNEG, and VCLAMP that trigger an error condition. When an error condition occurs, the VOUT pin is shorted to VSS. Table 7 lists the voltage levels shown in Figure 48. VPOS VDD ERROR VINH ERROR VNEG VDD VINH NORMAL NORMAL NORMAL 05448-048 DEVICE PROGRAMMING Digital Interface The digital interface allows the first stage gain, second stage gain, and output offset to be adjusted and allows desired values for these parameters to be permanently stored by selectively blowing polysilicon fuses. To minimize pin count and board space, a single-wire digital interface is used. The digital input pin, DIGIN, has hysteresis to minimize the possibility of inadvertent triggering with slow signals. It also has a pull-down current sink to allow it to be left floating when programming is not being performed. The pull-down ensures inactive status of the digital input by forcing a dc low voltage on DIGIN. A short pulse at DIGIN from low to high and back to low again, such as between 50 ns and 10 s long, loads a 0 into a shift register. A long pulse at DIGIN, such as 50 s or longer, loads a 1 into the shift register. The time between pulses should be at least 10 s. Assuming VSS = 0 V, voltages at DIGIN between VSS and 0.2 x VDD are recognized as a low, and voltages at DIGIN between 0.8 x VDD and VDD are recognized as a high. A timing diagram example, Figure 49, shows the waveform for entering code 010011 into the shift register. VCLAMP VDD VCLL ERROR VINL VSS ERROR VINL VSS ERROR VSS Figure 48. Voltage Regions at VPOS, VNEG, and VCLAMP that Trigger a Fault Condition Table 7. Typical VINL, VINH, and VCLL Values (VDD = 5 V) Voltage VINH VINL VCLL Min (V) 2.95 1.95 1.05 Typ (V) 3.0 2.0 1.1 Max (V) 3.05 2.05 1.15 VOUT Condition Short to VSS fault detection Short to VSS fault detection Short to VSS fault detection Rev. 0 | Page 18 of 28 AD8556 www..com tW1 tWS tW0 WAVEFORM 05448-049 tWS tWS tW0 tW0 tWS tW1 tWS tW1 CODE 0 1 0 0 1 1 Figure 49. Timing Diagram for Code 010011 Table 9. Timing Specifications Timing Parameter tw0 tw1 tws Description Pulse Width for Loading 0 into Shift Register Pulse Width for Loading 1 into Shift Register Width Between Pulses Specification Between 50 ns and 10 s 50 s 10 s Table 10. 38-Bit Serial Word Format Field No. 0 1 Bits 0 to 11 12 to 13 Description 12-Bit Start of Packet 1000 0000 0001 2-Bit Function 00: Change Sense Current 01: Simulate Parameter Value 10: Program Parameter Value 11: Read Parameter Value 2-Bit Parameter 00: Second Stage Gain Code 01: First Stage Gain Code 10: Output Offset Code 11: Other Functions 2-Bit Dummy 10 8-Bit Value Parameter 00 (Second Stage Gain Code): 3 LSBs Used Parameter 01 (First Stage Gain Code): 7 LSBs Used Parameter 10 (Output Offset Code): All 8 Bits Used Parameter 11 (Other Functions) Bit 0 (LSB): Master Fuse Bit 1: Fuse for Production Test at Analog Devices Bit 2: Parity Fuse 12-Bit End of Packet 0111 1111 1110 2 14 to 15 3 4 16 to 17 18 to 25 5 26 to 37 A 38-bit serial word is used, divided into 6 fields. Assuming each bit can be loaded in 60 s, the 38-bit serial word transfers in 2.3 ms. Table 10 summarizes the word format. Field 0 and Field 5 are the start-of-packet field and end-ofpacket field, respectively. Matching the start-of-packet field with 1000 0000 0001 and the end-of-packet field with 0111 1111 1110 ensures that the serial word is valid and enables decoding of the other fields. Field 3 breaks up the data and ensures that no data combination can inadvertently trigger the start-of-packet and end-of-packet fields. Field 0 should be written first and Field 5 written last. Within each field, the MSB must be written first and the LSB written last. The shift register features power-on reset to minimize the risk of inadvertent programming; power-on reset occurs when VDD is between 0.7 V and 2.2 V. Rev. 0 | Page 19 of 28 AD8556 www..com Initial State Initially, all the polysilicon fuses are intact. Each parameter has the value 0 assigned (see Table 11). Table 11. Initial State Before Programming Second Stage Gain Code = 0 First stage gain code = 0 Output offset code = 0 Master fuse = 0 Second Stage Gain = 17.5 First stage gain = 4.0 Output offset = VSS Master fuse not blown At least 10 F (tantalum type) of decoupling capacitance is needed across the power pins of the device during programming. The capacitance can be on the programming apparatus as long as it is within 2 inches of the device being programmed. An additional 0.1 F (ceramic type) in parallel with the 10 F is recommended within 1/2 inch of the device being programmed. A minimum period of 1 ms should be allowed for each fuse to blow. There is no need to measure the supply current during programming. The best way to verify correct programming is to use the read mode to read back the programmed values. Then, remeasure the gain and offset to verify these values. Programmed fuses have no effect on the gain and output offset until the master fuse is blown. After blowing the master fuse, the gain and output offset are determined solely by the blown fuses, and the simulation mode is permanently deactivated. Parameters are programmed by setting Field 1 to 10, selecting the desired parameter in Field 2, and selecting a single bit with the value 1 in Field 4. As an example, suppose the user wants to permanently set the second stage gain to 50. Parameter 00 needs to have the value 0000 0011 assigned. Two bits have the value 1, so two fuses need to be blown. Since only one fuse can be blown at a time, this code can be used to blow one fuse: 1000 0000 0001 10 00 10 0000 0010 0111 1111 1110 The MOS switch that blows the fuse closes when the complete packet is recognized, and opens when the start-of-packet, dummy, or end-of-packet fields are no longer valid. After 1 ms, this second code is entered to blow the second fuse: 1000 0000 0001 10 00 10 0000 0001 0111 1111 1110 To permanently set the first stage gain to a nominal value of 4.151, Parameter 01 needs to have the value 000 1011 assigned. Three fuses need to be blown, and the following codes are used, with a 1 ms delay after each code: 1000 0000 0001 10 01 10 0000 1000 0111 1111 1110 1000 0000 0001 10 01 10 0000 0010 0111 1111 1110 1000 0000 0001 10 01 10 0000 0001 0111 1111 1110 To permanently set the output offset to a nominal value of 1.260 V when VDD = 5 V and VSS = 0 V, Parameter 10 needs to have the value 0100 0000 assigned. If one fuse needs to be blown, use the following code: 1000 0000 0001 10 10 10 0100 0000 0111 1111 1110 Finally, to blow the master fuse to deactivate the simulation mode and prevent further programming, use code: 1000 0000 0001 10 11 10 0000 0001 0111 1111 1110 There are a total of 20 programmable fuses. Since each fuse requires 1 ms to blow, and each serial word can be loaded in When power is applied to a device, parameter values are taken either from internal registers, if the master fuse is not blown, or from the polysilicon fuses, if the master fuse is blown. Programmed values have no effect until the master fuse is blown. The internal registers feature power-on reset, so the unprogrammed devices enter a known state after power-up. Power-on reset occurs when VDD is between 0.7 V and 2.2 V. Simulation Mode The simulation mode allows any parameter to be temporarily changed. These changes are retained until the simulated value is reprogrammed, the power is removed, or the master fuse is blown. Parameters are simulated by setting Field 1 to 01, selecting the desired parameter in Field 2, and the desired value for the parameter in Field 4. Note that a value of 11 for Field 2 is ignored during the simulation mode. Examples of temporary settings follow: * Setting the second stage gain code (Parameter 00) to 011 and the second stage gain to 50 produces: 1000 0000 0001 01 00 10 0000 0011 0111 1111 1110 * Setting the first stage gain code (Parameter 01) to 000 1011 and the first stage gain to 4.166 produces: 1000 0000 0001 01 01 10 0000 1011 0111 1111 1110 A first stage gain of 4.166 with a second stage gain of 50 gives a total gain of 208.3. This gain has a maximum tolerance of 2.5%. * Set the output offset code (Parameter 10) to 0100 0000 and the output offset to 1.260 V when VDD = 5 V and VSS = 0 V. This output offset has a maximum tolerance of 0.8%: 1000 0000 0001 01 10 10 0100 0000 0111 1111 1110 Programming Mode Intact fuses give a bit value of 0. Bits with a desired value of 1 need to have the associated fuse blown. Since a relatively large current is needed to blow a fuse, only one fuse can be reliably blown at a time. Thus, a given parameter value may need several 38-bit words to allow reliable programming. A 5.25 V (0.25 V) supply is required when blowing fuses to minimize the on resistance of the internal MOS switches that blow the fuse. The power supply voltage must not exceed the absolute maximum rating and must be able to deliver 250 mA of current. Rev. 0 | Page 20 of 28 AD8556 www..com 2.3 ms, the maximum time needed to program the fuses can be as low as 66 ms. Parity Error Detection A parity check is used to determine whether the programmed data of an AD8556 is valid, or whether data corruption has occurred in the nonvolatile memory. Figure 50 shows the schematic implemented in the AD8556. VA0 to VA2 is the 3-bit control signal for the second stage gain, VB0 to VB6 is the 7-bit control signal for the first stage gain, and VC0 to VC7 is the 8-bit control signal for the output offset. PFUSE is the signal from the parity fuse, and MFUSE is the signal from the master fuse. The function of the 2-input AND gate (Cell AND2) is to ignore the output of the parity circuit (PAR_SUM signal) when the master fuse has not been blown. PARITY_ERROR is set to 0 when MFUSE = 0. In the simulation mode, for example, parity check is disabled. After the master fuse has been blown, that is, after the AD8556 has been programmed, the output from the parity circuit (PAR_SUM signal) is fed to PARITY_ERROR. I0 VA0 VA1 VA2 VB0 VB1 VB2 VB3 VB4 VB5 VB6 VC0 VC1 VC2 VC3 VC4 VC5 VC6 VC7 IN01 IN02 IN03 IN04 IN05 IN06 IN07 IN08 IN09 IN10 IN11 IN12 IN13 IN14 IN15 IN16 IN18 IN17 EOR18 OUT DAT_SUM PFUSE IN1 When PARITY_ERROR is 0, the AD8556 behaves as a programmed amplifier. When PARITY_ERROR is 1, a parity error has been detected, and VOUT is connected to VSS. The 18-bit data signal (VA0 to VA2, VB0 to VB6, and VC0 to VC7) is fed to an 18-input exclusive-OR gate (Cell EOR18). The output of Cell EOR18 is the DAT_SUM signal. DAT_SUM = 0 if there is an even number of 1s in the 18-bit word; DAT_SUM = 1 if there is an odd number of 1s in the 18-bit word. Refer to Table 12 for examples. After the second stage gain, first stage gain, and output offset have been programmed, compute DAT_SUM and set the parity bit equal to DAT_SUM. If DAT_SUM is 0, the parity fuse should not be blown in order for the PFUSE signal to be 0. If DAT_SUM is 1, the parity fuse should be blown to set the PFUSE signal to 1. The code to blow the parity fuse is: 1000 0000 0001 10 11 10 0000 0100 01111111 1110. After setting the parity bit, the master fuse can be blown to prevent further programming, using the code: 1000 0000 0001 10 11 10 0000 0001 0111 1111 1110. I1 OUT IN2 EOR2 PAR_SUM MFUSE IN1 I2 OUT IN2 AND2 PARITY_ERROR Figure 50. Functional Circuit of AD8556 Parity Check Table 12. Examples of DAT_SUM Second Stage Gain Code 000 000 000 000 000 001 001 111 First Stage Gain Code 000 0000 000 0000 000 0000 000 0001 100 0001 000 0000 000 0001 111 1111 Output Offset Code 0000 0000 1000 0000 1000 0001 0000 0000 0000 0000 0000 0000 1000 0000 1111 1111 Number of Bits with 1 0 1 2 1 2 1 3 18 DAT_SUM 0 1 0 1 0 1 1 0 Rev. 0 | Page 21 of 28 05448-050 AD8556 www..com Signal PAR_SUM is the output of the 2-input exclusive-OR gate (Cell EOR2). After the master fuse is blown, set PARITY_ERROR to PAR_SUM. As mentioned earlier, the AD8556 behaves as a programmed amplifier when PARITY_ERROR = 0 (no parity error). On the other hand, VOUT is connected to VSS when a parity error has been detected, that is, when PARITY_ERROR = 1. It is theoretically possible, though very unlikely, for a fuse to be incompletely blown during programming, assuming the required conditions are met. In this situation, the fuse could have a medium resistance, neither low nor high, and a voltage of approximately 1.5 V could be developed across the fuse. Thus, the OTP cell could output Logic 0 or a Logic 1, depending on temperature, supply voltage, and other variables. To detect this undesirable situation, the sense current can be lowered by a factor of 4 using a specific code. The voltage developed across the fuse would then change from 1.5 V to 0.38 V, and the output of the OTP would be a Logic 0 instead of the expected Logic 1 from a blown fuse. Correctly blown fuses would still output a Logic 1. In this way, incorrectly blown fuses can be detected. Another specific code would return the sense current to the normal (larger) value. The sense current cannot be permanently programmed to the low value. When the AD8556 is powered up, the sense current defaults to the high value. The low sense current code is: 1000 0000 0001 00 00 10 XXXX XXX1 0111 1111 1110 The normal (high) sense current code is: 1000 0000 0001 00 00 10 XXXX XXX0 0111 1111 1110 Read Mode The values stored by the polysilicon fuses can be sent to the FILT/DIGOUT pin to verify correct programming. Normally, the FILT/DIGOUT pin is only connected to the second gain stage output via RF. During read mode, however, the FILT/DIGOUT pin is also connected to the output of a shift register to allow the polysilicon fuse contents to be read. Since VOUT is a buffered version of FILT/DIGOUT, VOUT also outputs a digital signal during read mode. Read mode is entered by setting Field 1 to 11 and selecting the desired parameter in Field 2. Field 4 is ignored. The parameter value, stored in the polysilicon fuses, is loaded into an internal shift register, and the MSB of the shift register is connected to the FILT/DIGOUT pin. Pulses at DIGIN shift out the shift register contents to the FILT/DIGOUT pin, allowing the 8bit parameter value to be read after seven additional pulses; shifting occurs on the falling edge of DIGIN. An eighth pulse at DIGIN disconnects FILT/DIGOUT from the shift register and terminates the read mode. If a parameter value is less than eight bits long, the MSBs of the shift register are padded with 0s. For example, to read the second stage gain, this code is used: 1000 0000 0001 11 00 10 0000 0000 0111 1111 1110 Since the second stage gain parameter value is only three bits long, the FILT/DIGOUT pin has a value of 0 when this code is entered, and remains 0 during four additional pulses at DIGIN. The fifth, sixth, and seventh pulses at DIGIN return the 3-bit value at FILT/DIGOUT, the seventh pulse returns the LSB. An eighth pulse at DIGIN terminates the read mode. Programming Procedure For reliable fuse programming, it is imperative to follow the programming procedure requirements, especially the proper supply voltage during programming. 1. When programming the AD8556, the temperature of the device must be between 10C to 40C. 2. Set VDD and VSS to the desired values in the application. Use simulation mode to test and determine the desired codes for the second stage gain, first stage gain, and output offset. The nominal values for these parameters are shown in Table 5, Table 6, Equation 2, and Equation 3; use the codes corresponding to these values as a starting point. However, since actual parameter values for given codes vary from device to device, some fine tuning is necessary for the best possible accuracy. One way to choose these values is to set the output offset to an approximate value, such as Code 128 for midsupply, to allow the required gain to be determined. Then set the second stage gain so the minimum first stage gain (Code 0) gives a lower gain than required, and the maximum first stage gain (Code 127) gives a higher gain than required. After choosing the second stage gain, the first stage gain can be chosen to fine tune the total gain. Finally, the output offset can be adjusted to give the desired value. After determining the desired codes for second stage gain, first stage gain, and output offset, the device is ready for permanent programming. Sense Current A sense current is sent across each polysilicon fuse to determine whether it has been blown. When the voltage across the fuse is less than approximately 1.5 V, the fuse is considered not blown, and Logic 0 is output from the OTP cell. When the voltage across the fuse is greater than approximately 1.5 V, the fuse is considered blown, and Logic 1 is output. When the AD8556 is manufactured, all fuses have a low resistance. When a sense current is sent through the fuse, a voltage less than 0.1 V is developed across the fuse. This is much lower than 1.5 V, so Logic 0 is output from the OTP cell. When a fuse is electrically blown, it should have a very high resistance. When the sense current is applied to the blown fuse, the voltage across the fuse should be larger than 1.5 V, so Logic 1 is output from the OTP cell. Rev. 0 | Page 22 of 28 AD8556 www..com Important: Once a programming attempt has been made for any fuse, there should be no further attempt to blow that fuse. If a fuse does not program to the expected state, discard the unit. The expected incidence rate of attempted but unblown fuses is very small when following the proper programming procedure and conditions. 3. Set VSS to 0 V and VDD to 5.25 V (0.25 V). Power supplies should be capable of supplying 250 mA at the required voltage and properly bypassed as described in the Programming Mode section. Use program mode to permanently enter the desired codes for the first stage gain, second stage gain, and output offset. Blow the parity bit fuse if necessary (see Parity Error Detection section). Blow the master fuse to allow the AD8556 to read data from the fuses and to prevent further programming. 4. Set VDD and VSS to the desired values in the application. Use read mode with low sense current followed by high sense current to verify programmed codes. 5. Measure gain and offset to verify correct functionality. 3. Use Table 5 or Equation 1 to set the first stage gain code CG1, so the first stage gain is nominally GA/G2. 4. Measure the resulting gain (GB). GB should be within 3% of GA. 5. Calculate the first stage gain error (in relative terms) EG1 = GB/GA - 1. 6. Calculate the error (in the number of the first stage gain codes) CEG1 = EG1/0.00370. 7. Set the first stage gain code to CG1 - CEG1. 8. Measure the gain (GC). GC should be closer to GA than to GB. 9. Calculate the error (in relative terms) EG2 = GC/GA - 1. 10. Calculate the error (in the number of the first stage gain codes) CEG2 = EG2/0.00370. 11. Set the first stage gain code to CG1 - CEG1 - CEG2. The resulting gain should be within one code of GA. Finally, determine the desired output offset: 1. Determine the desired output offset OA (using the measurements obtained from the simulation). 2. Use Equation 2 to set the output offset code CO1 such that the output offset is nominally OA. 3. Measure the output offset (OB). OB should be within 3% of OA. 4. Calculate the error (in relative terms) EO1 = OB/OA - 1. 5. Calculate the error (in the number of the output offset codes) CEO1 = EO1/0.00392. 6. Set the output offset code to CO1 - CEO1. 7. Measure the output offset (OC). OC should be closer to OA than to OB. 8. Calculate the error (in relative terms) EO2 = OC/OA - 1. 9. Calculate the error (in the number of the output offset codes) CEO2 = EO2/0.00392. 10. Set the output offset code to CO1 - CEO1 - CEO2. The resulting offset should be within one code of OA. Determining Optimal Gain and Offset Codes First, determine the desired gain: 1. Determine the desired gain, GA (using the measurements obtained from the simulation). 2. Use Table 6 to determine G2, the second stage gain, such that (4.00 x 1.04) < (GA/G2) < (6.4/1.04). This ensures the first and last codes for the first stage gain are not used, thereby allowing enough first stage gain codes within each second stage gain range to adjust for the 3% accuracy. Next, set the second stage gain: 1. Use the simulation mode to set the second stage gain to G2. 2. Set the output offset to allow the AD8556 gain to be measured, for example, use Code 128 to set it to midsupply. Rev. 0 | Page 23 of 28 AD8556 www..com EMI/RFI PERFORMANCE Real world applications must work with ever increasing radio/magnetic frequency interference (RFI and EMI). In situations where signal strength is low and transmission lines are long, instrumentation amplifiers such as AD8556 are needed to extract weak, small differential signals riding on common-mode noise and interference. Additionally, wires and PCB traces act as antennas and pick up high frequency EMI signals. The longer the wire, the larger the voltage it picks up. The amount of voltages picked up is dependent on the impedances at the wires, as well as the EMI frequency. These high frequency voltages are then passed into the in-amp through its pins. All instrumentation amplifiers can rectify high frequency out-of-band signals. Unfortunately, the EMI/RFI rectification occurs because amplifiers do not have any significant common-mode rejection above 100 kHz. Once these high frequency signals are rectified, they appear as dc offset errors at the output. AD8556 features internal EMI filters on the VNEG, VPOS, FILT and VCLAMP pins. These built-in filters on the pins limit DIGIN VDD EMI FILTER LOGIC VDD EMI FILTER 1 +IN 2 -IN VSS P2 EMI FILTER A3 1 +IN P1 VDD -IN 1 +IN VNEG EMI FILTER 2 +IN -IN VSS A2 OUT 3 the interference bandwidth, and provide good RFI suppression without reducing performance within the pass-band of the in-amp. A functional diagram of AD8556 along with its EMI/RFI filters is shown in Figure 51. AD8556 has built-in filters on its inputs, VCLAMP, and filter pins. The first-order low-pass filters inside the AD8556 are useful to reject high frequency EMI signals picked up by wires and PCB traces outside the AD8556. The most sensitive pin of any amplifier to RFI/EMI signal is the non-inverting pin. Signals present at this pin appear as common-mode signals and create problems. The filters built at the input of the AD8556 have two different bandwidths: common and differential mode. The commonmode bandwidth defines what a common-mode RF signal sees between the two inputs tied together and ground. The EMI filters placed on the input pins of the AD8556 reject EMI/RFI suppressions that appear as common-mode signals. VCLAMP VDD A5 1 2 +IN OUT -IN VSS 3 DAC VSS 3 A1 R5 R2 P4 R7 OUT VPOS VDD 3 VDD RF EMI FILTER 1 +IN 2 -IN VSS A4 OUT 3 R3 2 OUT -IN VSS VOUT R1 R4 P3 R6 AD8556 FILT/DIGOUT VSS Figure 51. Block Diagram Showing EMI/RFI Built-In Filters Rev. 0 | Page 24 of 28 05448-053 AD8556 www..com In order to show the benefits that the AD8556 brings to new applications where EMI/RFI signals are present, a part was programmed with a gain of 70, dc offset = 2.5 V, to produce VOUT = 0 V. A test circuit like that shown in Figure 52 was used. Figure 52 simulates the presence of a noisy common-mode signal, and Figure 53 shows the response dc values at VOUT. +2.5V U3 1 2 3 0 4 VDD FILT/DIGOUT DIGIN VNEG VSS VOUT VCLAMP VPOS 8 7 6 5 -2.5V inputs, VPOS (that is, +IN ) and VNEG (that is, -IN). Figure 54 shows the circuit used to test for AD8556 EMI/RFI susceptibility. The part is programmed as stated previously during the common-mode testing. +2.5V U2 1 VDD VSS VOUT VCLAMP VPOS 8 7 6 5 V2 05448-052 -2.5V 2 FILT/DIGOUT 3 0 4 DIGIN VNEG VOUT 2.5V VOUT 2.5V 0 AD8556 200mV p-p AD8556 Figure 54. Test Circuit to Show AD8556 Performance Exposed to Differential Mode RFI/EMI Signals V3 05448-051 VARIABLE The response of AD8556 to EMI/RFI differential signals is shown in Figure 55. 600 400 200 0 AD8556 Figure 52. Test Circuit to Show AD8556 Performance Exposed to Common-Mode RFI/EMI Signals DC OFFSET (mV) 100 DEVIATION FROM DC OUTPUT (mV) -200 -400 -600 -800 -1000 -1200 0 200 400 600 FREQUENCY (MHz) 800 1000 05448-055 80 NON-EMI PROTECTED SOLUTION 60 NON-EMI PROTECTED SOLUTION 40 20 -1400 0 AD8556 05448-054 Figure 55. Response of AD8556 to EMI/RFI Differential Signals 400 600 800 1000 -20 0 200 FREQUENCY (MHz) Figure 53. DC Offset Values at VOUT Caused by Frequency Seep of Input The differential bandwidth defines the frequency response of the filters with a differential signal applied between the two To make a board robust against EMI, the leads at VPOS and VNEG should be as similar as possible. In this way, any EMI received by the VPOS and VNEG pins will be similar (that is, a common-mode input), and rejected by the AD8556. Furthermore, additional filtering at the VPOS and VNEG pins should give a better reduction of unwanted behavior compared with filtering at the other pins. Rev. 0 | Page 25 of 28 AD8556 www..com OUTLINE DIMENSIONS 5.00 (0.1968) 4.80 (0.1890) 8 5 4.00 (0.1574) 3.80 (0.1497) 1 6.20 (0.2440) 4 5.80 (0.2284) 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) 1.75 (0.0688) 1.35 (0.0532) 0.50 (0.0196) x 45 0.25 (0.0099) 0.51 (0.0201) COPLANARITY SEATING 0.31 (0.0122) 0.10 PLANE 8 0.25 (0.0098) 0 1.27 (0.0500) 0.40 (0.0157) 0.17 (0.0067) COMPLIANT TO JEDEC STANDARDS MS-012-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN Figure 56. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) 4.00 BSC SQ 0.60 MAX 0.60 MAX 0.65 BSC 3.75 BSC SQ 0.75 0.60 0.50 13 12 16 1 PIN 1 INDICATOR 2.25 2.10 SQ 1.95 0.25 MIN 1.95 BSC PIN 1 INDICATOR TOP VIEW (BOTTOM VIEW) EXPOSED PAD 4 5 9 8 12 MAX 1.00 0.85 0.80 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM SEATING PLANE 0.30 0.23 0.18 0.20 REF COPLANARITY 0.08 COMPLIANT TO JEDEC STANDARDS MO-220-VGGC Figure 57. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 4 mm x 4 mm Body, Very Thin Quad (CP-16-4) Dimensions shown in millimeters ORDERING GUIDE Model AD8556ARZ1 AD8556ARZ-REEL1 AD8556ARZ-REEL71 AD8556ACPZ-R21 AD8556ACPZ-REEL1 AD8556ACPZ-REEL71 AD8556ARZ-EVAL1 1 Temperature Range -40C to +140C -40C to +140C -40C to +140C -40C to +140C -40C to +140C -40C to +140C Package Description 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 16-Lead LFCSP_VQ 16-Lead LFCSP_VQ 16-Lead LFCSP_VQ Evaluation Board Package Option R-8 R-8 R-8 CP-16-4 CP-16-4 CP-16-4 Z = Pb-free part. Rev. 0 | Page 26 of 28 AD8556 www..com NOTES Rev. 0 | Page 27 of 28 AD8556 www..com NOTES (c)2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05448-0-5/05(0) Rev. 0 | Page 28 of 28 |
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